1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device, wherein a silicide is formed to lower the source/drain sheet resistance.
2. Related Art
Due to ever-increasing device density and ever-decreasing device dimensions in accordance with Moore's Law, design and research/development of super-sized integrated circuits encounters many complicated technical problems, such as RC delay, gate leakage current, poly depletion, and gate resistance.
Moreover, the resistances (Rc, Rch, Rov, or source/drain series resistance Rsd etc.) considered in the design of a metal oxide silicon field effect transistor (MOSFET) vary significantly with device dimensions, wherein a graded doping profile with high resistance is generated due to well implant engineering and thermal budget. Further, due to dimension scaling, the area of the contact window is reduced, and Rc is increased accordingly. However, as the dimensions are reduced, it is also very important to take the source/drain sheet resistance into consideration in addition to the above resistances.
For example, U.S. Pat. No. 5,612,253 discloses a related art, wherein the contact windows are etched; next, a Ti metal layer is sputtered; then, nitrogen gas is fed into an annealing furnace; and three annealing control steps are conducted, such that Ti and the substrate react to generate a silicide. The silicide layer is used to lower the contact window resistance. However, as the substrate is consumed during the process of forming the silicide layer, the source/drain sheet resistance (Rcsd) is increased. Moreover, the surface of the Ti metal layer and the nitrogen gas contact and react with each other, so as to generate TiN to function as a barrier layer, thus preventing the WF4 and Ti from reacting to form a volcano effect when the metal is filled into the contact windows.
Referring to FIGS. 1 and 2, they are partial cross-sectional view of a semiconductor device according to another prior art. The semiconductor device is, for example, a metal oxide semiconductor (MOS) formed on a silicon substrate 11. The silicon substrate 11 has a gate region 12 and two junction regions 13, 14. An oxide layer 121 is further formed between the gate region 12 and the silicon substrate 11. With selective epitaxial growth (SEG) technology, a silicon layer or SiGe epitaxial layer 15 is grown on the gate region 12 and two junction regions 13, 14.
Further, a metal layer 16 is deposited by sputtering to cover the gate region 12 and the two junction regions 13, 14. Then, rapid thermal annealing process (RTP) is conducted to convert the silicon or SiGe expitaxy grown on the gate region 12 and the two junction regions 13, 14 into a silicide 17.
With the reduction of device dimensions, the proportion of the source/drain sheet resistance in the series resistance of the whole device becomes higher and higher. Therefore, due to the reduction of device dimensions, the source/drain sheet resistance has gradually become an urgent technical problem to be solved.